1. Field of the Invention
This invention relates to a dynamic read-write random access memory, and more particularly to a dynamic read-write random access memory fabricated of MOS transistors.
2. Description of the Prior Art
Various electrical circuits such as a processor and a memory have been integrated on a semiconductor chip due to recent prominent developments in semiconductor techniques.
A dynamic read-write random access memory, hereinafter abbreviated as a "DRAM", is a semiconductor memory of the type admitting of not only the reading but also the writing of data. It is adapted to a large capacity memory for storing data in the form of stored electric charge, because it employs a memory cell formed of a small number of transistors.
FIG. 1 is one example circuit diagram of a memory cell that includes a transistor and a capacitor. This memory cell is most used in a DRAM because of its small number of transistors.
In fact, this memory cell includes a capacitor (C) for storing data and a MOS transistor (T.sub.t) for transferring data.
Data is stored in the capacitor (C) connected between a voltage supply terminal (101) that supplies one voltage level (e.g., 5 v) and a drain terminal (102) of the transistor (T.sub.t).
A writing operation of the memory cell is as follows:
(i) a source terminal (103) of the transistor (T.sub.t) is supplied with one voltage level, for example, a high voltage level (i.e. "1", e.g., 5 v) correspnnding to the data to be written; PA1 (ii) a gate terminal (104) of the transistor (T.sub.t) is supplied with a high voltage level (e.g. 5 v) to the selected memory cell such that the voltage level of the drain terminal (102) becomes a "1" voltage level, corresponding to the voltage level on the source terminal (103); and PA1 (iii) the voltage level of the gate terminal (104) changes from the high voltage level to a low voltage level, such that the transistor (T.sub.t) becomes nonconductive.
On the other hand, a reading operation from the memory cell is made by detecting (i.e. sensing) a change of the voltage level of the source terminal (103) of the transistor (T.sub.t) at a time when the gate terminal (104) of the transistor (T.sub.t) is supplied the high voltage level to select the memory cell.
Although the above operation is explained by using one memory cell, an actual DRAM has many memory cells. Many source terminals of the memory cells are connected to a bit line, and as a result, a large stray capacitor occurs between the bit line and the semiconductor substrate. The capacitance of the stray capacitor is usually much larger than the capacitor (C). So, the change of the voltage level of the source terminal (103) of the transistor (T.sub.t) is very small when the memory cell is selected. For that reason, the prior art DRAM usually has a sense amplfiier and a precharge circuit.
FIG. 2 shows a DRAM using the memory cell as shown in FIG. 1. Source terminals of the memory cells (111, 113, . . . ) are connected to a bit line (B). On the other hand, source terminals of the memory cells (112, 114, . . . ) are connected to a bit line (B). Gate terminals of the memory cells (111, 112, 113, 114, . . . ) are respectively connected to word lines (W.sub.1, W.sub.2, W.sub.3, W.sub.4, . . . ). The bit line (B) is connected to a dummy cell (121), and the other bit line (B) is connected to another dummy cell (122). The gate terminal of the transistor (T.sub.t) of the dummy cell (121) is connected to a dummy word line (DW.sub.l). On the other hand, the gate terminal of the transistor (T.sub.t) of the dummy cell (122) is connected to a dummy word line (DW.sub.2). The two bit line (B, B) are connected to a sense amplifier (131) and a precharge circuit (132).
There will now be described by reference to FIG. 2 and FIG. 3 operation of the DRAM shown in FIG. 2.
A. Reading operation under the condition that the memory cell (111) stores "1".
(i) At time t.sub.0.
Voltage levels of all of the word lines (W.sub.1, W.sub.2, W.sub.3, W.sub.4, . . . ) and all of the dummy word lines (DW.sub.1, DW.sub.2) are V.sub.SS (e.g., 0 v). All of the transistors of the memory cells (111, 112, 113, 114, . . . ) and the dummy cells (121, 122) are nonconductive and none of cells (111, 112, 113, 114, . . . , 121, 122) are selected.
The voltage level of a sense latch signal (SL) is high and is supplied to a gate terminal of a transistor (T.sub.SL). Sense amplifier (131) is thus operative.
The voltage level (V.sub.B) of the bit line (B) is V.sub.SS because the sense amplifier (131) is flip-flop type differential amplifier.
The voltage level (V.sub.B) of the other bit line (B) is nearly V.sub.CC because electric charge precharged prior to a reading cycle is stored in the stray capacitor existing between the bit line (B) and the semiconductor substrate on which the DRAM is integrated.
(ii) At time t.sub.1.
At time t.sub.1, the voltage level of the precharge signal (PG) becomes high. Then, transistors (T.sub.PG1, T.sub.PG2, T.sub.PG3) of the precharge circuit (132) become conductive. As a result, the bit lines (B, B) are precharged to "1".
On the other hand, the voltage level of the sense latch signal (SL) is low and the transistor (T.sub.SL) becomes nonconductive. As a result, the two bit lines (B, B) are electrically separated from the V.sub.SS terminal.
As shown in FIG. 3, the voltage level (V.sub.B) of the bit line (B) drops a little. This change is due to phenomenon that current runs from the bit line (B) to the bit line (B) when the transistor (T.sub.PG2) becomes conductive. When another precharge circuit is used, the voltage level (V.sub.B) may be shown by the broken line in FIG. 3.
(iii) At time t.sub.2.
Then the voltage level of the precharge signal (PG) becomes low.
(iv) At time t3.
The voltage level of the word line (W.sub.1) connected to the memory cell (111) changes from "0" to "1". The voltage level of the dummy word line (DW.sub.2) connected to the dummy cell (122) is also changes from "0" to "1". The signal "V.sub.W" shown in the FIG. 3 illustrates the voltage level of the word line (W.sub.l) and that of the dummy word line (DW.sub.2).
(v) At time t.sub.4.
The word liee (W.sub.l) is sufficiently charged to "1". This means that the memory cell (111) is selected. The dummy word line (DW.sub.2) is also sufficiently charged to "1", and the dummy cell (122) is selected too. (Prior to time t.sub.4, the transistor (T.sub.d) becomes conductive and a voltage level of the node between the transistor (T.sub.t) and the capacitor (C') is brought to around V.sub.SS.)
If leakage current does not flow through the transistor (T.sub.t) of memory cell (111), the voltage level of the drain terminal, which is connetted to the capacitor (C), of the memory cell (111) is "V.sub.CC -V th", where Vth is the threshold voltage of the transistor (T.sub.t). On the other hand, the voltage level of the source terminal, which is connected to the bit line (B), of the memory cell (111) is kept at V.sub.CC. Therefore, the transistor (T.sub.t) remains nonconductive. That is to say, the voltage level (V.sub.B) does not change even though the memory cell (111) is selected.
The voltage level of the drain terminal, which is connected to the capacitor (C), of the dummy cell (122) is nearly V.sub.SS. On the other hand, the voltage level of the source terminal, which is connected to the bit line (B), of the dummy cell (122) is nearly V.sub.CC because the bit line (B) remains V.sub.CC.
This means that a potential difference between the drain and gate terminals of the transistor (T.sub.t) of the dummy cell (122) is higher than a threshold voltage of the transistor (T.sub.t) of the dummy cell (122). Therefore, this transistor (T.sub.t) becomes conductive. As a result, precharged electric carrier on the bit line (B) is distributed not only by the capacitor (C') of the dummy cell (122) but also by the stray capacitor of the bit line (B) .
This phenomenon is illustrated by using the following equations under the conditions that "Cp" is the stray capacitor of bit line (B) and "V.sub.x " is the voltage level of the bit line (B) after the distribution. EQU C.sub.p (v.sub.CC -V.sub.SS)=(C.sub.p +C')V.sub.x
Therefore, ##EQU1##
The capacitance of the stray capacitor (Cp) is usually ten to hundreds times as large as that of the capacitor (C') because many memory cells are connected to the bit line (B).
On the other hand, the capacitance (C') of the dummy cell (122) is usually one half that of the memory cell (111), i.e., C'=C/2. Accordingly, ##EQU2##
Now, ##EQU3## is represented by .DELTA.V. Then, ##EQU4##
It is understood from the above equations that the voltage level of the bit line (B) drops by .DELTA.V/2 from V.sub.CC. (See the solid line at time t.sub.5 in FIG. 3)
(vi) At time t.sub.5.
The voltage level of the sense latch signal (SL) becomes high. Then the transistor (T.sub.SL) becomes conductive and the sense amplifier (131) starts its operation.
The sense amplifier (131) is a differential amplifier including a pair of cross-coupled MOS transistors (T.sub.l, T.sub.2) having a common source and having their gates connected to each other's drain. The transistor (T.sub.2) becomes conductive and the transistor (T.sub.l) does not because the voltage level at the gate terminal of the transistor (T.sub.2) is higher than that of the transistor (T.sub.l). The differential is .DELTA.V/2.
Then, the voltage level of the bit line (B) is brought to V.sub.SS prior to time t.sub.6 as shown in FIG. 3.
As a result, the potential difference between the two bit lines (B, B) becomes V.sub.CC -V.sub.SS.
(vii) At time t.sub.6.
The voltage levels of the word line (W.sub.l) and the dummy word line (DW.sub.2) becomes V.sub.SS.
B. Reading Operation under the condition that the memory cell (111) strres "0".
Operation at time t.sub.O through t.sub.3 under the condition that the memory cell (111) stores "0" is almost the same as that under the condition that the memory cell (111) stores "1", and the explanation thereof is therefore omitted.
(v) At time t.sub.4.
The word line (W.sub.l) is sufficiently charged to V.sub.CC and the memory cell (111) is selected. The dummy word line (DW.sub.2) is also sufficiently charged to V.sub.CC. And the dummy cell (122) is selected.
The voltage level of the drain terminal, which is connected to the capacitor (C) of the memory cell (111) is nearly V.sub.SS because the memory cell (111) stores a "0". On the other hand, the voltage level of the source terminal connected to the bit line (B) of the memory cell (111) is V.sub.CC because the voltage level of the bit line (B) remains "1". Then, the potential difference between the drain and gate terminals of the transistor (T.sub.t) of the memory cell (111) becomes higher than the threshold voltage of this transistor (T.sub.t), and the transisoor (T.sub.t) becomes conductive. Therefore, precharged electric carrier of the bit line (B) is distributed not only by the capacitor (C) of the memory cell (111) but also by the stray capacitor of the bit line (B).
This phenomenon is illustrated by using the following equations under the conditions that "Cp" is the stray capacitor of the bit line (B), where the values of stray capacitors of the bit line (B) and (B) are generally the same, and "V.sub.x " is the voltage level of the bit line (B) after the distribution. ##EQU5##
It is apparent from the above equations that the voltage level of the bit line (B) drops by .DELTA.V from V.sub.CC. (See the dotted line at time t.sub.4 in FIG. 3.)
Operation of the dummy cell (122) under the condition that the memory cell stores "0" is almost the same as that under the condition that the memory cell stores "1". That is to say, the voltage level of the bit line (B) is dropped by .DELTA.V/2 from V.sub.CC. (See the dotted line at time t.sub.5 in FIG. 3.)
(vi) At time t.sub.5.
The voltage level of the sense latch signal (SL) becomes high, and the transistor (T.sub.SL) becomes conductive. Then the sense amplifier (131) starts its operation. The transistor (T.sub.l) becomes conductive and the transistor (T.sub.2) does not because the voltage level of the gate terminal of the transistor (T.sub.l) is higher than that of the transistor (T.sub.2) by the differential amount of .DELTA.V/2.
Then, the voltage level of the bit line (B) is brought to V.sub.SS prior to time t.sub.6 as shown in FIG. 3.
As a result, the potential difference between the two bit lines (B, B) becomes V.sub.CC -V.sub.SS .DELTA.V/2.
(vii) At time t.sub.6.
The voltage levels of the word line (Wl) and the dummy word line (DW.sub.2) become "0".
The capacity of a semiconductor memory like the abov DRAM has increased as micronization techniques have advanced. For example, a 1M-bit DRAM is made of small MOS (insulated gate type) transistors whose gates are 1 .mu.m to 1.5 .mu.m long. Moreover, a 4M-bit DRAM which will be developed in the future may be formed of MOS transistors whose gate lengths are reduced to about 0.8 .mu.m, and a 16M-bit DRAM which will be developed in the future may be mdde of MOS transistors whose gate lengths are reduced to about 0.5 .mu.m. Each memory cell of such a large-capacity DRAM includes two elements, i.e., a capacitor for storing data and a MOS transistor for transfering data as shown in FIG. 4(a). The shorter the gate length and effective channel length of the transfer MOS transistor, the more difficult it is to control the threshold voltage of the MOS transistor due to the short-channel effect and the more ambiguous a boundary line betwee a gate oxide (141) and a field oxide (142) (see FIG. 4(b)) becomes. Consequently, the subthreshold current of the MOS transistor flows too much to be negligible. That is, characteristics of data being stored deteriorate.
FIG. 5 shows the characteristics of V.sub.g vs. .sqroot.I.sub.D of a MOS transistor. V.sub.g is the gate voltage (V.sub.g) and I.sub.d is the drain current (I.sub.d) under the conditions that the transistor gate length is 1.0 .mu.m, the channel length is 0.8 .mu.m, the gate oxide thickness is 150 .ANG., and the substrate density is 5.times.10.sup.15 [cm.sup.-3 ]. As shown in FIG. 5, a subthreshold current flows even though V.sub.g is 0 V. This means that any data stored in a nonselected memory cell disappear due to the subthreshold current. One approach to solve this problem is to refresh the data before the data thoroughly disappears. Indeed, where there is no problem with the subthreshold current, data stored in memory cells is usually refreshed because leakage current runs through the capacitor or through the pn junction. However, where the subthreshold current is a problem and ten to hundreds times as large as the leakage current, data stored in the memory cells are required to be refreshed to solve the problem due to the subthreshold current ten to hundreds times as frequently as to solve the problem due to the ordinary leakage current. Actually however, it is impossible to refresh so often.
Another approach to solve the problem due to the subthreshold current involves ion implantation, where ions of an acceptor impurity are implanted into the channel region of the N-channel transfer transistor and also into the region below this channel region in a high concentration to suppress the subthreshold current or the short-channel effect. If this measure is taken, the effective threshold voltage changes due to the reverse bias effect of the N-channel transistor, the channel mobility of the transistor is deteriorated, or the source-drain junction capacitance of the transistor for transfering data increases (see FIG. 4(a)). Consequently, the capacitance of the stray capacitor will increase.